1. Field of the Invention
The invention presents a method of manufacturing integrated circuit chips that partiallyjoins an integrated circuit wafer to a supporting wafer at a limited number of joining points.
2. Description of the Related Art
Within this application several publications are referenced by arabic numerals within parentheses. Full citations for these, and other, publications may be found at the end of the specification immediately preceding the claims. The disclosures of all these publications in their entireties are hereby expressly incorporated by reference into the present application for the purposes of indicating the background of the present invention and illustrating the state of the art. The below-referenced U.S. Patents disclose embodiments that were satisfactory for the purposes for which they were intended. The disclosures of the below-referenced prior U.S. Patents, in their entireties, are hereby expressly incorporated by reference into the present invention for purposes including, but not limited to, indicating the background of the present invention and illustrating the state of the art.
In 1965, Dr. Gordon Moore, then Director of Research and Development for Fairchild Semiconductor, made the observation that the number of transistor devices per integrated circuit had been doubling every couple of years since the creation of the first integrated circuits in the late 1950's and that he expected the trend to continue for the foreseeable future. This observation was dubbed “Moore's Law” by the trade press. Now almost 40 years later, despite numerous dire predictions of fundamental obstacles, unrelenting industry efforts towards every-increasing semiconductor density have effectively affirmed Dr. Moore's prophetic observation, and the trend is still expected to continue unabated for the foreseeable future. The process of reducing semiconductor device size to increase integrated circuit density is generally referred to as “scaling”.
In fact, because of the scaling, silicon based process technologies have facilitated a tremendous increase in the frequency range of operation for both digital and analog circuits. The fast transistors combined with low defect densities open the door to integration of complex high-speed micro-electronic systems on a single chip, which was simply not feasible or economical before. Unfortunately, such ultra-high-frequency integrated systems mandate a paradigm shift in the packaging methodology and thermal managements. Conventional chip/module cooling schemes can no longer handle the thermal dissipation of this new generation of chips. A new cooling concept to effectively remove heat from the chip and module is urgently needed.
There are many motivations for thinning a die. The primary motivation is to improve the thermal conductivity. As wafer thickness is increased, thermal dissipation from the back side of the wafer presents a challenge. The situation is aggravated when a buried oxide layer is presented on a SOI (Silicon on Insulator) wafer which is used to enhance device performance.
On the other hand, in order to enable ultra high density 3-Dimensional stacked packaging of flash memory and SRAM IC for portable electronics, thin dies are necessary to save space. To thin down a die, especially after a wafer's C4 solder balls or wire-bond pads are formed, wafer tested, diced, and picked is definitely not an easy task. In the past, a special set up to polish down the back side of the die with the front size fully protected is one of the conventional approaches. This method is not only expensive, but also results in potential reliability concerns, and is therefore not manufacturable.
One example of temporary bonding, called reversible bonding was proposed by et al. and titled “Reversible Wafer Bonding for Reliable Compound Processing”. They suggested the use of wax or dry film adhesives to bond a wafer to a silicon carrier to enhance the mechanical strength during processing. The two substrates are separated after the processing is completed. Similar methods are used in U.S. Pat. No. 4,962,879 and U.S. Pat. No. 6,010,591 (incorporated herein by reference), both are methods to bond two wafers during transportation, handling and processing. They are separated after processing. Unfortunately, all the conventional reversible bonding methods are not suitable for high-temperature processing. During semiconductor processing, especially during steps such as diffusion, oxidation and annealing, the wafer substrate must endure temperature as high as 1100° C. All the reversible bonding methods so far can only sustain a temperature limit of 150° C. Neither method is cost-effective or reliable. Both etching and mechanical polishing are time consuming. The chemicals used for etching and polishing are prone to attack circuits and C4 balls on the front side of the die. A good protective coating and secure holding to avoid damage is a challenge. Besides, neither method is able precisely stop at a predetermined thickness during the thinning process.